1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, and in particular, a method for manufacturing a small semiconductor device, represented by a wafer level chip scale package (WCSP).
2. Description of Related Art
In an integrated circuit package in which semiconductor elements such as a semiconductor integrated circuit are packaged, demand for miniaturization and thinning is increasing. Recently, WCSP (Wafer Level Chip Scale Packaging), in which ball-shaped terminals are arranged in a grid on the surface of a semiconductor element, has been promoted, mainly in the field of semiconductor integrated circuit packaging, in which thinning is particularly demanded. As this semiconductor device manufacturing method, a manufacturing method has been proposed in which rewiring is provided on a silicon wafer on which a pad electrode, an interlayer insulation film, and an underlying metal layer have been sequentially formed, and forming a column electrode on the surface of the rewiring; the underlying metal layer is subsequently removed, and resin sealing is performed (see Japanese Patent Application Laid-Open (JP-A) No. 2005-38979).
However, in recent years, as a result of increasing demand to further miniaturize wafer level chip scale packages, the width and spacing of internal rewiring has decreased, and demands for reducing allowed values for outer dimensions have increased. In a conventional processing method, when an underlying metal layer is removed by, for example, etching, rewiring is also eroded. Further, if a post electrode having a height of 100 μm or more above the wafer surface is present, the flow of etching liquid at the wafer surface is not uniform. As a result, variations in etching rate at the wafer surface occur, which may cause irregularities in the shape of rewiring, and thus in a conventional process method, it has not been possible to satisfy allowed values for outer dimensions. Moreover, when excessive etching is performed in order to prevent the generation of etching residue, since rewiring is also etched, irregularities in rewiring become even greater, which is problematic. These problems are explained in detail below with reference to FIGS. 7-10.
FIGS. 7A-10 are sectional views of a conventional semiconductor device manufacturing method. First, as shown in FIG. 7A, aluminum (Al) electrode pad 103 is formed on oxidation film 102 which itself is formed on semiconductor substrate 101. After forming surface protection film 104 and interlayer insulation film 105, a through hole is opened above electrode pad 103.
Next, as shown in FIG. 7B, on the surface of electrode pad 103 and interlayer insulation film 105, underlying metal adhesive layer 106, formed from Ti or the like, and underlying metal antioxidant layer 107, formed from Cu or the like, are sequentially laminated by a sputter method or the like.
Subsequently, as shown in FIG. 7C, a photosensitive resin layer is covered over the entire surface, and a developing process for pattern-forming and pattern-opening of the photosensitive resin layer is performed, forming a pattern of photosensitive resin film 108. Next, taking underlying metal antioxidant layer 107 as a common electrode, copper is electrodeposited in an electroplating method to form rewiring 109 which extends from electrode pad Al 103 to a portion forming a copper column electrode (described below).
Next, as shown in FIG. 8A, photosensitive resin film 108 is removed by dissolving or the like, and as shown in FIG. 8B, photosensitive resin film 110 is adhered over the entire surface of underlying metal antioxidant layer 107, and a hole portion for forming column electrode 111 is formed by an exposing and developing process. Then, taking underlying metal antioxidant layer 107 as a common electrode, column electrode 111 is formed by electrodepositing copper in an electroplating method.
As shown in FIG. 8C, photosensitive resin film 110 is removed by dissolving or the like, and underlying metal antioxidant layer 107 and underlying metal adhesive layer 106 are removed by etching at an appropriate time. Finally, as shown in FIG. 9, a sealing resin 112 is formed such that the surface of column electrode 111 is exposed, and a soldering terminal 113 is formed by a reflow process on column electrode 111. The wafer is diced into pieces and a semiconductor device like that shown in FIG. 10A is manufactured.
In the above semiconductor device manufacturing method according to conventional techniques, when underlying metal antioxidant layer 107 and underlying metal adhesive layer 106 are removed in the process performed between FIG. 8B and FIG. 8C, since the flow of an etching liquid is not uniform due to column electrode 111, irregularities occur in etching.